1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device applied chiefly to an inverter circuit or the like.
2. Description of the Background Art
An inverter circuit that converts a DC (direct current) voltage into an AC (alternating current) voltage is used for operating a load such as induction motor. To the inverter circuit, an insulated gate bipolar transistor (IGBT) is applied as a switching device.
For a semiconductor device of this type, an SOI (Silicon On Insulator) substrate is used. In the SOI substrate, an N− semiconductor layer is formed on a main surface of a semiconductor substrate with an insulating film interposed between the main surface and the N− semiconductor layer. In the N− semiconductor layer, a first N-type impurity region is formed to a predetermined depth from the surface of the N− semiconductor layer. A first P-type impurity region is formed to surround the first N-type impurity region laterally and from below. On a surface of a portion of the first P-type impurity region that is located between the first N-type impurity region and the N− semiconductor layer, a gate electrode is formed with a gate insulating film interposed between the surface and the gate electrode. Further, an emitter electrode is formed to contact respective surfaces of the first P-type impurity region and the first N-type impurity region.
In a predetermined region of the N− semiconductor layer located at a distance from the first P-type impurity region, a second P-type impurity region is formed from the surface of the N− semiconductor layer to a predetermined depth. A collector electrode is formed to contact the surface of the second P-type impurity region. In another predetermined region of the N− semiconductor layer located at a predetermined distance on a side where the first P-type impurity region is located, with respect to the second P-type impurity region, a second N-type impurity region is formed from the surface of the N− semiconductor layer to a predetermined depth to serve as a stopper against a depletion layer. The emitter electrode, the collector electrode, and the gate electrode constitute corresponding electrodes of the IGBT, respectively.
While the semiconductor device is in an OFF state, a depletion layer expands mainly toward the N− semiconductor layer, from the interface between the first P-type impurity region and the N− semiconductor layer. At this time, the impurity concentration and the thickness of the N− semiconductor layer can be adjusted to convert the whole of the N− semiconductor layer into a depletion layer. Under the condition that the electric field is substantially uniform in the surface region of the N− semiconductor layer, a maximum breakdown voltage is obtained.
Under this condition, if the distance (space) between the emitter (electrode) and the collector (electrode) is increased, finally the breakdown voltage of the whole is restricted due to electric field concentration on a portion of the N− semiconductor layer that is located directly below the collector (electrode). In the case of the above-described IGBT, the breakdown voltage is determined by the punch-through phenomenon in which an end of the depletion layer contacts the second P-type impurity region, or determined by a leakage current of a parasitic PNP transistor formed of the second P-type impurity region, the N− semiconductor layer, and the first P-type impurity region.
Conventionally, with the purpose of increasing the breakdown voltage of a semiconductor device, a technique of providing the second N-type impurity region to serve as a stopper against the depletion layer as described above has generally been employed. A technique of extending the collector electrode toward the emitter side has also been employed.
The inventor of the present invention has proposed in Japanese Patent Laying-Open No. 06-188438 a semiconductor device including a dielectric portion with a predetermined thickness provided between a semiconductor substrate and an N− semiconductor layer. In this semiconductor device, the thickness of a part of the dielectric portion located directly below a collector electrode is made larger than the thickness of the remaining part of the dielectric portion. In the structure of the semiconductor substrate, the dielectric portion, and the N− semiconductor layer (laminate structure), the electric field intensity of the semiconductor substrate, the dielectric portion, and the N− semiconductor layer each is an inverse of the ratio between respective dielectric constants of them. Thus, a dielectric portion of a larger thickness can be provided to further increase a voltage drop in the dielectric portion, and accordingly decrease a voltage drop in a portion of the N− semiconductor layer which is located directly below the collector (electrode) and into which the depletion layer is to expand. Consequently, the margin of the breakdown voltage of the whole semiconductor device is increased and the breakdown voltage characteristic of the semiconductor device can be improved.
As seen from the above, for the conventional semiconductor devices, various proposals have been advanced in order to improve the breakdown voltage characteristic. Improvement of the breakdown voltage has been demanded for the semiconductor devices, not only for the IGBT but also for a p-channel MOS (Metal Oxide Semiconductor) transistor (PMOS) applied as a device for generating a signal to cause the IGBT to perform a switching operation.